A method has been developed in recent years whereby a plurality of solder balls is arrayed in the form of a matrix on the surface of a wiring board, and a semiconductor chip is mounted on the solder balls in order to obtain a smaller semiconductor device. Examples of such a semiconductor device are FCBGA (Flip Chip Ball Grid Array) and WLCSP (Wafer Level Chip Size Package). Also known is a multilayer wiring board in which a plurality of wiring-embedded resin layers is layered, a build-up wiring board with a so-called core member, and a package board includes MLTS (Multi Layer Thin Substrate) (brand name) structures.
Nevertheless, conventional methods have the problems described below. In other words, silicon, which is the material of the semiconductor chip, and the resin that forms the wiring board have mutually different coefficients of thermal expansion. For this reason, warping is generated in the semiconductor device, and force is applied to the solder balls because the shrinkage of the semiconductor chip and the shrinkage of the wiring board are mutually different when the semiconductor device is cooled to room temperature, even when the semiconductor chip is mounted on the wiring board so that force is not applied during mounting. Also, the solder balls may experience fatigue fracturing and become disconnected when the semiconductor device repeatedly undergoes heating and cooling cycles due to heat generated by the operation of the semiconductor chip and changes in the outside temperature.
Conventionally, attempts have been made to avoid this problem and improve the connection reliability of a semiconductor device by forming the wiring board from a resin that is as rigid as possible. This is intended to minimize warping of the semiconductor device and deformations of the wiring board by increasing the rigidity of the wiring board. In Patent Document 1, for example, a method is disclosed that uses an insulation material that has a modulus of elasticity of 10 GPa or higher as the material of the wiring board.
[Patent Document 1] Japanese Laid-Open Patent Application No. 2002-198462